Gram-scale StarChip components | 4 processors

Aug 01, 2016 13:43 Breakthrough Initiatives Posted on: Breakthrough Initiatives

Apr 17, 2016 05:51john.hayden1@gmail.comPosted on: Breakthrough Initiatives
"Moore's Law may not be the feature size limiter. Particle implantation damage becomes more serious to smaller geometry devices - already, at 55nm and below (16nm is state of the art), single particles can disrupt 4-8 adjacent SRAM cells in the friendly terrestrial environment - which requires interleaving and muxing of data words in the physical SRAM layout even with ECC.

So: smaller feature size requires increasing redundancy, which increases area. At some point these may balance, i.e. reductions in features require bigger total survivable chip area."

Answer:
This is an excellent point. Smaller feature size may not be desirable for the electronics on the StarChip. Thankfully, we have quite a lot of area to work with on the sail. The nominal plan is to have many redundant copies of the electronics onboard. There may well be an optimal tradeoff between feature size and the number of instantiations of each electronic subsystem on the nanocraft.

– Zac Manchester, Breakthrough Initiatives

Aug 01, 2016 13:44 Breakthrough Initiatives Posted on: Breakthrough Initiatives

Apr 18, 2016 19:14Mitch FagenPosted on: Breakthrough Initiatives
"What about the effect the acceleration might have on the electronic components and connections? I've read in news stories about this proposal that the acceleration is estimated to be approximately 60,000 g. Is it possible to make microchips, a motherboard, a camera, etc., that could survive such a force?"

Answer:
Thankfully solid-state electronics are extremely robust to large accelerations. In fact, the electronics in current “smart” artillery rounds routinely survive accelerations comparable to the 60,000 g envisioned for the nanocraft.

– Zac Manchester, Breakthrough Initiatives

Jan 08, 2017 12:17 michael.million@sky.com Posted on: Centauri Dreams

Sensors have now been built that can survive 200 000 g, I think when this concept is up and running 60 000 g will be on the conservative side.

http://www.memsic.com/accelerometers/MXC4005XC

Jan 19, 2017 12:58 michael.million@sky.com Posted on: Centauri Dreams

If we use an optical grade SO2 backing we could use cores made of silicon as communication highways via laser light instead of wires, it may weight less and allow more bandwidth, this should make good use of weight.

https://www.osapublishing.org/oe/fulltext.cfm?uri=oe-18-5-5305&id=196205

https://en.wikipedia.org/wiki/Subwavelength-diameter_optical_fibre

https://phys.org/news/2012-01-narrowest-wires-silicon-current-capability.html




Feb 01, 2017 18:55 John Gold Posted on: Breakthrough Initiatives

http://www.atmel.com/about/news/release.aspx?reference=tcm:26-66628

Atmel’s SAM L21 family consumes less than 940nA with full 40kB SRAM retention, real-time clock and calendar and 200nA in the deepest sleep mode.

SAM L21 peripherals that support Sleepwalking—a technology that enables peripherals to request a clock when needed to wake-up from sleep modes and perform tasks without having to power up the CPU Flash and other support systems.

Atmel’s proprietary Event System that allows peripherals to work together to solve complex tasks using minimal gates and also the lowest possible power.

Feb 02, 2017 18:46 Breakthrough Initiatives Posted on: Breakthrough Initiatives

RE:
"Jan 19, 2017 12:58 michael.million@sky.com Posted on: Centauri Dreams
If we use an optical grade SO2 backing we could use cores made of silicon as communication highways via laser light instead of wires, it may weight less and allow more bandwidth, this should make good use of weight.

https://www.osapublishing.org/oe/fulltext.cfm?uri=oe-18-5-5305&id=196205

https://en.wikipedia.org/wiki/Subwavelength-diameter_optical_fibre

https://phys.org/news/2012-01-narrowest-wires-silicon-current-capability.html";

Answer:
Thank you for your consideration. These are very good approaches and we will consider them when the design matures. There is a balance between beginning the design work for the star chip and developing the Photon Engine. Currently we are strictly focused on three items, the photon engine, sail and communications back to earth.

– Pete Klupar, Breakthrough Starshot

Feb 28, 2017 11:00 Breakthrough Initiatives Posted on: Breakthrough Initiatives

RE:
"Feb 01, 2017 18:55 John Gold Posted on: Breakthrough Initiatives

http://www.atmel.com/about/news/release.aspx?reference=tcm:26-66628
Atmel’s SAM L21 family consumes less than 940nA with full 40kB SRAM retention, real-time clock and calendar and 200nA in the deepest sleep mode.

SAM L21 peripherals that support Sleepwalking—a technology that enables peripherals to request a clock when needed to wake-up from sleep modes and perform tasks without having to power up the CPU Flash and other support systems.

Atmel’s proprietary Event System that allows peripherals to work together to solve complex tasks using minimal gates and also the lowest possible power."

Answer:
Thank you for your thoughts and recommendations. The SAM L21 device family is very popular and powerful. It will be a device like this that will enable the star chip. We are planning on these devices to continue to improve and possibly get to below 10nA for operational power.

– Pete Klupar, Breakthrough Starshot

Mar 23, 2017 14:57 michael.million@sky.com Posted on: Centauri Dreams

It may be a good idea to use graphene as an electrical conductors on the surface of the dark side of the sail, firstly it has very good damage resistance properties and secondly can carry high currents, it is also very, vey light weight. With the sail design it would be better to have a distributed 'ebrain' which would reduce the chances of catastrophic failure of the system.

https://www.eurekalert.org/pub_releases/2016-12/vuot-gat122116.php

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